The present invention relates to a semiconductor integrated circuit device and more particularly to a technology suitably applied to a semiconductor integrated circuit device having a Static Random Access Memory (SRAM). An example description about SRAM is given in IEDM (International Electron Devices Meeting) Technical Digest, pp. 39-42, 1992.
An SRAM as a semiconductor memory device includes memory cells, each consisting of a flip-flop circuit and two transfer MISFETs (Metal Insulator Semiconductor Field-Effect Transistors) at intersections between complementary data lines and word lines.
The flip-flop circuit of the memory cell is formed as an information storage section that stores one bit of information. The flip-flop circuit is formed, for example, of a pair of CMOS (Complementary Metal Oxide Semiconductor FET) inverters. Each of the CMOS inverters consists of an n-channel driver MISFET and a p-channel load MISFET. The transfer MISFETs formed are of n-channel type.
An equivalent circuit of the SRAM memory cell made up of these six MISFETs is shown in FIG. 36.
As shown in the figure, one of the CMOS inverters INV.sub.1 includes a driver MISFET Qd.sub.1 and a load MISFET Qp.sub.1 while the other CMOS inverter INV.sub.2 includes a driver MISFET Qd.sub.2 and a load MISFET Qp.sub.2. The input and output terminals of these paired CMOS inverters INV.sub.1, INV.sub.2 are cross-coupled through a pair of interconnects (hereinafter referred to as local interconnection lines) L.sub.1, L.sub.2 to form a flip-flop circuit. One end of the flip-flop circuit is connected to a power supply voltage V.sub.CC and the other end to a reference voltage V.sub.SS.
The operation of the above circuit is described below. When the output node A of one CMOS inverter INV.sub.1 is at high potential "H," the driver MISFET Qd.sub.2 conducts causing the output node B of the other CMOS inverter INV.sub.2 to go low "L." Hence, the driver MISFET Qd.sub.1 turns off, holding the output node A at high potential "H." In other words, a latch circuit consisting of the paired CMOS inverters INV.sub.1, INV.sub.2 cross-coupled with each other retains the states of these output nodes, i.e. holding information while being impressed with the supply voltage.
One of the source region and the drain region of the transfer MISFET Qt.sub.1 is connected to the input/output terminal of one of the CMOS inverters INV.sub.1 of the flip-flop circuit, while the other of the source and drain region is connected to one of the complementary data lines (first data line D.sub.1). One of the source and drain region of the transfer MISFET Qt.sub.2 is connected to the input/output terminal of the second CMOS inverter INV.sub.2 of the flip-flop circuit, while the other of the source and drain region is connected to the other complementary data line (second data line D.sub.2).
The two transfer MISFETs Qt.sub.1, Qt.sub.2 have their gate electrodes connected with a word line WL, which controls the conduction and non-conduction of the transfer MISFETs Qt.sub.1, Qt.sub.2. That is, when the word line WL is at high potential "H," the transfer MISFETs Qt.sub.1, Qt.sub.2 are turned on, connecting the latch circuit with the complementary data lines, so that the potential states (either "H" for high or "L" for low) of the node A and node B appear on the complementary data line and is read out as memory cell information. On the contrary, it is possible to forcibly apply the potentials of the complementary data lines to the node A and node B.
FIG. 37 illustrates one example of a pattern layout of the SRAM memory cell shown in the above equivalent circuit.
The six MISFETs making up the memory cell, i.e. transfer MISFETs Qt.sub.1, Qt.sub.2, driver MISFETs Qd.sub.1, Qd.sub.2 and load MISFETs Qp.sub.1, Qp.sub.2, each have a source-drain region formed in the semiconductor substrate and a gate electrode formed on top of the semiconductor substrate. The transfer MISFETs Qt.sub.1, Qt.sub.2 have a common gate electrode 50 formed integrally with the word line WL. The gate electrode 50 (word line WL) is normally formed of a polycrystalline silicon film, or a polycide film which is a laminated film of a polycrystalline silicon film and a high melting point metal silicide film.
The driver MISFET Qd.sub.1 and the load MISFET Qp.sub.1, both making up the first CMOS inverter INV.sub.1 of the flip-flop circuit, have a common gate electrode 51. The driver MISFET Qd.sub.2 and the load MISFET QP.sub.2, making up the second CMOS inverter INV.sub.2, have a common gate electrode 52. These gate electrodes 51, 52 and the gate electrode 50 (word line WL) for the transfer MISFETs Qt.sub.1, Qt.sub.2 are formed of the same polycrystalline silicon film or polycide film, which is fabricated by the same process.
Deposited over the gate electrodes 50, 51, 52 through an interlayer insulating film not shown are a power source voltage line 53, a reference voltage line 54 and a pair of local interconnection lines L.sub.1, L.sub.2 cross-coupling the input/output terminals of the paired CMOS invertors INV.sub.1, INV.sub.2. The power source voltage line 53, the reference voltage line 54 and the paired local interconnection lines L.sub.1, L.sub.2 are formed of the same metal film (aluminum alloy, tungsten, etc.) which is fabricated by the same process.
The power source voltage line 53 is connected to the source regions of the load MISFETs Qp.sub.1, Qp.sub.2 via connecting holes 55, 55; and the reference voltage line 54 is connected to the source regions of the driver MISFETs Qd.sub.1, Qd.sub.2 through connecting holes 56, 56. One end of the local interconnection line L.sub.2 is connected to the drain region of the load MISFET QP.sub.2 through a connecting hole 57; and the other end is connected through a connecting hole 58 to the drain region of the driver MISFET Qd.sub.2 (one of the source and drain region of the transfer MISFET Qt.sub.2) and to the gate electrode 51 of the driver MISFET Qd.sub.1 (load MISFET Qp.sub.1). One end of the local interconnection line L.sub.1 is connected through a connecting hole 59 to the drain region of the load MISFET Qp.sub.1 and the gate electrode 52 of the driver MISFET Qd.sub.2 (load MISFET Qp.sub.2); and the other end is connected through a connecting hole 60 to the drain region of the driver MISFET Qd.sub.1 (one of the source and drain region of the transfer MISFET Qt.sub.1).
Deposited over the power source voltage line 53, the reference voltage line 54 and the local interconnection lines L.sub.1, L.sub.2 are a pair of complementary data lines (first data line D.sub.1 and second data line D.sub.2) which are formed of a second metal film (aluminum alloy, tungsten, etc.). The first data line D.sub.1 is connected to the other of the source and drain region of the transfer MISFET Qt.sub.1 through a connecting hole 61 and a pad layer 62. The second data line D.sub.2 is connected to the other of the source and drain region of the transfer MISFET Qt.sub.2 through a connecting hole 63 and the pad layer 62. The pad layer 62 is formed of the same first layer metal film that is used to form the power source voltage line 53, the reference voltage line 54 and the local interconnection lines L.sub.1, L.sub.2.
As described above, in the SRAM, the gate electrodes of the six MISFETs--which make up the memory cell--are formed of the first layer polycrystalline silicon film (or polycide film) 50, 51, 52 formed on the surface of the semiconductor substrate. The power source voltage line 53, the reference voltage line 54 and the paired local interconnection lines L.sub.1, L.sub.2 are formed of the first metal film deposited over the polycrystalline silicon film (or polycide film). The paired complementary data lines D.sub.1, D.sub.2 are formed of the second layer metal film deposited over the first layer metal film.